Latest Articles
Replaying Stimuli in an UVM Verification Environment
Introduction This work addresses the inability to reproduce, port, or shorten a UVM test failure outside of the exact seed, simulator, and testbench that originally
VCD2Activity – Application for activity estimation in digital circuits during the design stage
If you’ve ever worked in hardware design and/or verification, you know that discovering a power problem late in the design is a nightmare. You’ve already
Development of a Reusable AXI-Lite UVC
AXI-Lite is a lightweight, powerful subset of the AXI protocol from the ARM AMBA family, used for register access and peripheral communication within an SoC,
AMIQ Education Program
Replaying Stimuli in an UVM Verification Environment
Introduction This work addresses the inability to reproduce, port, or shorten a UVM test failure outside of the exact seed, simulator, and testbench that originally
Development of a Reusable AXI-Lite UVC
AXI-Lite is a lightweight, powerful subset of the AXI protocol from the ARM AMBA family, used for register access and peripheral communication within an SoC,
Regression Failure Triage using ECTB Parameter Clustering
All scripts, architectures, implementation details and usage examples discussed in this article are available in the project GitHub repository: amiq_plcust. Introduction Debugging is a consistent
Events
Overview FPGA Front Runner
Last week I attended the “FPGA Front Runner: FPGA Verification Strategies” conference hosted by Alpinum Consulting.In this blog post I aim to share an overview
Highlights of DVCon EU 2023
This post presents some of the highlights of the technical program AMIQ consultants enjoyed attending at DVCon Europe 2023 (14-16 November, on site). Overall we
AMIQ’s Externally Controlled Testbench Architecture
This article is a follow-up on the paper presented at DVCon EU 2022 entitled How creativity kills reuse – A modern take on UVM/SV TB
Tutorials
Replaying Stimuli in an UVM Verification Environment
Introduction This work addresses the inability to reproduce, port, or shorten a UVM test failure outside of the exact seed, simulator, and testbench that originally
VCD2Activity – Application for activity estimation in digital circuits during the design stage
If you’ve ever worked in hardware design and/or verification, you know that discovering a power problem late in the design is a nightmare. You’ve already
Development of a Reusable AXI-Lite UVC
AXI-Lite is a lightweight, powerful subset of the AXI protocol from the ARM AMBA family, used for register access and peripheral communication within an SoC,
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