Highlights of DVCon US 2016

DVCon US (Feb. 29th – Mar 3rd, 2016, San Jose, California) has concluded another successful edition.

There were a lot of interesting tutorials, panels and technical sessions, with SV/UVM still being a major focus. There was also a clear emphasis on portable stimuli and the associated standard developed by Accellera’s Portable Stimuli Working Group (PSWG), which AMIQ is a member of.

Below are the highlights of the technical program I attended and enjoyed.


Tutorial 1: Preparing for IEEE UVM Plus UVM Tips and Tricks (Doug Perry – Doulos, Srivatsa Vasudevan – Synopsys) – The first two parts of the tutorial present tips and tricks on how to recognize and debug common errors while using the UVM package. The last part talks about the changes to the upcoming IEEE version of the UVM standard.

Tutorial 2: SVA Advanced Topics: SVAUnit and Assertions for Formal – Of course :-) Me and my colleague Andra Radu enjoyed talking about SVA verification using AMIQ’s open-source SVAUnit framework. More details can be found here. The slides are available here.

Tutorial 3: Cut Your Design Time in Half with Higher Abstraction (Bob Condo, Dirk Seynhaeve – Intel, Frederic Doucet – Qualcomm, Peter Frey – Mentor, Mike Meredith – Cadence) – The Accellera SystemC Synthesis Working Group (SSWG) presented a SystemC synthesizable subset and how to use it to write synthesizable models at a higher level of abstraction compared with traditional RTL. The tutorial concluded with practical usage examples by Intel and Altera.

Tutorial 9: Back to Basics: Doing Formal the Right Way (Joe Hupcey, Mark Eslinger, Doug Smith – Mentor) – A very informative tutorial on formal verification. It contains tips on how to write SVAs for formal as well as a guide to efficiently set up the formal engine and track your formal verification progress with coverage-based analysis.

Technical papers with presentation

1.2  Adapting the UVM Register Abstraction Layer for Burst Access (Mark Villalpano – General Dynamics Mission Systems) – This paper shows how to perform front-door burst read or write accesses using UVM RAL’s uvm_reg.read/write().

5.1 SystemVerilog Interface Classes – More Useful Than You Thought (Stan Sokorac – ARM) – (Best Paper – 2nd Place) – This paper by Stan Sokorac from ARM® shares real-life experience using interface classes. Two interesting use cases are: Pseudo-Multiple-Inheritance and Analysis Port Alternative.

5.2 Generic Programming in SystemVerilog (Mark Glasser – NVIDIA) – This paper shows how to develop re-usable environments using SystemVerilog without coding the low-level details. With this in mind, the authors developed the SystemVerilog Extension (SVX) library to enable generic programming features that SystemVerilog lacks.

8.2. Design Patterns by Example for SystemVerilog Verification Environments Enabled by SystemVerilog 1800-2012 (Eldon G. Nelson – Intel) (Best Paper – 1st Place) – This paper presents design pattern examples adapted from the “Head First Design Patterns” book originally written for Java. The patterns were ported to SystemVerilog keeping them as close as possible to the original implementation. The goal is to illustrate that many software design patterns can be implemented using SystemVerilog 1800-2012 and to show their usefulness in verification environments.

10.2 Regressions in the 21st Century – Tools for Global Surveillance (Venkataramanan Srinivasan, David Crutchfield, James F. Roberts, Tushar Gupta – Cypress Semiconductor) – This paper describes a system, built and utilized at Cypress Semiconductor, which gathers metrics across company-wide projects and makes them available to anyone on demand. It discusses how the metrics are gathered, where they are stored, and how they are accessed.

10.3 Optimal Usage of the Computer Farm for Regression Testing (Daniel Hansson, Patrik Granath – Verifyter AB) – This paper presents a costs and benefits analysis of computer farm resources used for regressions.

11.1 A 360 Degree View of UVM Events – A Case Study (Deepak Kumar E V, Sathish Dadi, Vikas Billa – elitePLUS Semiconductors Technologies) – Reset or interrupt handling, register modeling or inter-component communication are just a few of the UVM event use cases presented in this paper.

Technical papers with poster

4P.14 How Do You Verify Your Verification Components (Joshua W. Rensch – Superion Technology, Neil Johnson – XtremeEDA Corp) (Best Poster – 3rd Place) – Unit Testing verification with the SVUnit framework.

4P.23 EASI2L: A Specification Format for Automated Block Interface Generation and Verification (Chintan Kaur – Rensselaer Polytechnic Institute, Ravi Narayanaswami, C. Richard Ho – Google) – The authors present the results of their interviews with a selection of designers from their department about the interfaces/protocols they use. They propose a set of interface types and a specification format that can describe real interfaces based on these types. The paper also describes a tool (written in Go) that generates design and verification code from the interface specification. Unfortunately, the source code is not released as part of this paper.

Hot Topics

Portable Stimuli were discussed throughout the entire conference, starting from the daily sponsored luncheons to the keynote held by Mentor CEO, Walden C. Rhines. Portable stimuli were covered in technical presentations, posters, tutorials and the ESL panel.

Although it is not a new subject, HLS (High-Level Synthesis) was also a hot topic in my opinion, being discussed throughout tutorials, presentations and the ESL panel.

The SVUnit User Group lunch on Wednesday was a good opportunity to share ideas and experience with the engineers who are using unit testing as part of their verification flow. On top of that, the feedback we got on the SVAUnit framework makes me feel that unit testing is gaining momentum in hardware verification.


The conference definitely sets the bar high in terms of technical program diversity, premium content and networking opportunities.

I invite you to contribute your thoughts on the conference.


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