Latest Articles
AES UVC – A UVM Implementation
Cryptography is no longer just a mechanism used by the military or government officials to secure sensitive information. Over the years, it has evolved into
How to use clone() and copy() in SystemVerilog
When developing a verification environment using SystemVerilog and the UVM methodology, I often encounter the need to either clone a class instance using the clone()
UVM Packer Size Limitation: The 4KB Problem
In UVM-based verification environments, uvm_packer is a powerful utility for converting class objects to bit streams and vice versa. It’s commonly used for serialization and
AMIQ Education Program
Regression Failure Triage using ECTB Parameter Clustering
All scripts, architectures, implementation details and usage examples discussed in this article are available in the project GitHub repository: amiq_plcust. Introduction Debugging is a consistent
A Hands-off Control Algorithm HDL Implementation Using Vitis HLS
Fuel is a vital resource in many engineering applications. This is especially the case of aerospace applications, where resources are strictly limited. Moreover, if resupplying
Design and Verification Hands-on Learning
On 10 May, I participated in a session of design and verification project presentations at the Faculty of Electronics and Computer Science, Transilvania University of
Events
Overview FPGA Front Runner
Last week I attended the “FPGA Front Runner: FPGA Verification Strategies” conference hosted by Alpinum Consulting.In this blog post I aim to share an overview
Highlights of DVCon EU 2023
This post presents some of the highlights of the technical program AMIQ consultants enjoyed attending at DVCon Europe 2023 (14-16 November, on site). Overall we
AMIQ’s Externally Controlled Testbench Architecture
This article is a follow-up on the paper presented at DVCon EU 2022 entitled How creativity kills reuse – A modern take on UVM/SV TB
Tutorials
AES UVC – A UVM Implementation
Cryptography is no longer just a mechanism used by the military or government officials to secure sensitive information. Over the years, it has evolved into
How to use clone() and copy() in SystemVerilog
When developing a verification environment using SystemVerilog and the UVM methodology, I often encounter the need to either clone a class instance using the clone()
UVM Packer Size Limitation: The 4KB Problem
In UVM-based verification environments, uvm_packer is a powerful utility for converting class objects to bit streams and vice versa. It’s commonly used for serialization and
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