Tudor recommends us to take advantage of the e-language features to define similar vr_ad registers instead of using copy/paste:
VerificationGentleman: Experimental Cures for Flattened Register Definitions in vr_ad
Then he shows us how to implement side effects of read/write operations using vr_ad’s indirect_access() method:
VerificationGentleman: Using indirect_access(…) in vr_ad
The same Gentleman tutors us on how to handle multiple instances of vr_ad registers:
VerificationGentleman: Working with Multiple Instances of vr_ad Registers
Keisuke Shimizu helps you discover name space rules:
ClueLogic: Hidden Gems of SystemVerilog – 2. Name spaces
Cadence presents the power of e-language reflection in a 3 part series. This is a must read for juniors and seniors alike:
Cadence: Generic Dynamic Runtime Operations With e Reflection: Part 1 Part 2 Part3
Do you need an Ethernet packet library? Cristian provides the source code for SystemVerilog and SystemC:
AMIQ Blog: amiq_eth – The Ethernet Packet Library for SystemVerilog and SystemC
Daniel and Andra serve us a “Hello World!”-class tutorial on how to connect a SystemVerilog environment with Octave:
AMIQ Blog: How to Connect SystemVerilog with Octave
Get a glimpse and take the pulse of the first edition of DVCon Europe by reading Stefan’s birds-eye (re)view:
AMIQ Blog: A Birds-Eye View of DVCon Europe
Here it is an easy way to decipher what timescale is used by RTL modules:
AMIQ Blog: How to print `timescale in Verilog, SystemVerilog and VHDL
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