A Birds-Eye View of DVCon Europe

I finally found some time to write about the first edition of DVCon-Europe, which took place on 14-15th of October, 2014, in Munich.

The content

What I liked most at DVCon Europe was conference’s focus on content that addressed interesting and often intriguing technical topics. Below you can find the summary for a few presentations that really tug me and my colleagues in.
On a different note, I noticed that Open Source projects were more present than before. I could also read between the lines that Virtual Prototyping is getting more attention. SystemVerilog is always present in some way.

UVM SystemC and UVM SystemC Birds of a Feather Session

It looks like there is work in progress on the UVM SystemC but no one can tell when the first draft will be released to the public. A Birds of a Feather session followed later on the day bringing the industry and Accellera members face to face to discuss about the future of UVM-SystemC. However, there was no clear roadmap and or decision on the ownership: should the community take control, like with any other Open Source project, or should the Accellera committee manage it’s development? Time will tell, yet the industry is definitely eager to have it as soon as possible.

Introduction to Next Generation Verification Language – Vlang

Puneet Goel, the creator of the Vlang library, delivered a very energetic and passionate presentation. The Vlang library is an Open Source library over the D-language. Besides the fact it is based on a modern programming language (think reflection, annotations, generic programming), it also supports most of the UVM features and a BDD constraint solver. Another plus for the library is native multicore support. Coverage collection is on the roadmap.
This presentation showed there is the possibility of a better future than SystemVerilog and that from time to time we should reconsider the status of the existing verification languages. I think that a community driven Vlang together with a number of VIPs and support tools has the potential to overtake SystemVerilog.
I only wonder how can one convince the verification community to chip in and contribute to Vlang? How will EDA’s big three react to the development of an Open Source verification language?

CRAVE 2.0: The Next Generation Constrained Random Stimulus Generator for SystemC

Leaving aside creator’s stage fright, I consider that Mr Hoang M. Le, the creator of CRAVE 2.0, had one of the most compelling presentations. The SystemC Verification Library (aka SCV) currently implements a BDD-based constraint solver which has some limitations when it comes to solve large and/or complex sets of constraints. CRAVE 2.0 is a SMT-based solver that supports soft constraints and distribution constraints on top of a better scalability. This library could also give some boost to Vlang if they manage to integrate it.
You can download the CRAVE 2.0 here.

Algorithm Verification with Open Source and SystemVerilog

This was a good tutorial about on how you can hook-up SystemVerilog and Octave, which can also be extended to other Open Source tools. You can download the code here and there is also a tutorial available here.

The Universal Translator – A Fundamental UVM Component for Networking Protocols

The author presented a reusable, simple to use component that can save you time with protocol layers stacking.

Reboot your Reset Methodology: Resetting Anytime with the UVM Reset Package

Uwe Sim, one of the UVM contributors, illustrated how one can support multiple reset using UVM phases.

Advanced UVM and Virtual Prototyping using SystemC TLM-2.0

Although not exact news, these were very appreciated tutorials on UVM and SystemC TLM-2.0, by seniors and juniors alike.

The location

The venue was set up at Hilton Munich City Hotel, in the immediate vicinity of the English Garden park, a big plus for those who wanted to relax a bit in the evening. Also the commuting to/from the airport was easy.
The food and beverages served were good and in abundance and what else could you expect from a Bavarian location.
The venue space seemed to be a little bit overcrowded. Probably the organisers didn’t expect to have that much traffic.

Conclusions

Congratulations to the organisers and everyone involved in organising the conference and the exhibition!!! It was a valuable experience for AMIQ’s entire team. I believe that DVCon Europe has the potential to become a landmark conference in the European hardware design and verification community. We are certainly planning to participate as an active contributor to the tutorial/paper sessions next year .