How to print `timescale in Verilog, SystemVerilog and VHDL

Sometimes you need to make sure the correct time unit and precision are applied for each module down the instance tree, especially when there are different timescale directives in different modules and timescale arguments are used.

Print `timescale in Verilog, SystemVerilog

Use $printtimescale(path) simulator directive:

// timescale
`timescale 1ns/10ps

// top testbench module
module tb();

   // DUT instance
   dut dut_i();

   initial begin
      $printtimescale($root.tb); // prints the timescale of this module
      $printtimescale($root.tb.dut_i);// prints the timescale dut_i module instance
      $printtimescale($root.tb.dut_i.cpu_i);// prints the timescale dut_i.cpu_i module instance
   end 

endmodule

Print `timescale in VHDL

For VHDL you need to wrap the initial begin end statement in a dummy module:

module timescale_printer();
   initial begin
      $printtimescale($root.tb); // prints the timescale of this module
      $printtimescale($root.tb.dut_i);// prints the timescale dut_i module instance
      $printtimescale($root.tb.dut_i.cpu_i);// prints the timescale dut_i.cpu_i module instance
   end
endmodule

and instantiate it:

-- VHDL library declarations
library ieee;
use ieee.std_logic_1164.all;

LIBRARY DUT;
USE DUT.ALL;

LIBRARY tb;
USE tb.all;

-- declaration of tb entity
ENTITY tb IS
END;

-- implementation of the testbench
architecture rtl of tb is

-- declaration of timescale_printer component
COMPONENT timescale_printer is PORT ();
END COMPONENT timescale_printer;

-- declaration of dut component
COMPONENT dut is PORT ();
END COMPONENT dut;

begin

-- instance of the DUT; I skipped signal connections for the example's simplicity sake
dut_i : dut PORT_MAP();

-- instance of the timescale_printer component
timescale_printer_i : timescale_printer PORT MAP();

end rtl;

Results

The output of a run should be similar to:

Time scale of (tb) is  1ps /  1fs
Time scale of (tb.dut_i) is  1ps /  1ps
Time scale of (tb.dut_i.cpu_i) is  1ns /  10ps

Notes

If you are not at ease with timescales, you can take a 2 minute tutorial here.

I omitted DUT’s port declarations and connections for brevity.