SystemVerilog/UVM code reuse is reaching the next level. Andrei Vintilă and Sergiu Duda have developed a framework/architecture called Externally Controlled Testbench (aka ECTB), initially presented at DVCon Europe 2022 under the name How creativity kills reuse – A modern take on UVM/SV TB architectures. Now, as promised, the authors have published the User Guide on how to make use of the framework. The complete source code can be found on AMIQ’s GitHub.
Verification Gentleman has set on a path for another experiment around UVM. This time he wants to create UVM tests dynamically. It is a nice step-by-step insight into the inner workings of the UVM as well. Read more on his blog. The code can be found here.