Yet another way of connecting the testbench components to the interface containing the signals. Learn more about accessor classes and parametrization in the article How To Reduce the Number of VIP Instances using Accessor Classes
We have a new entry on our radar: VerificationLand. Mark Glasser displays his view of an SVlogical way of writing code. You can see it as tips&tricks for writing SystemVerilog code. He wrote another article about assumptions in verification. It can be very difficult to deal with assumptions. They might be hidden behind a piece of code or behind a verification plan. Take your time to read the articles and don’t make any assumptions.
Did you ever wondered what’s the difference between Verilog reg, Verilog wire and SystemVerilog logic? Jason Yu from VerilogPro takes this question and brings an eloquent answer to it:Verilog reg, Verilog wire, SystemVerilog logic. What’s the difference?
Here is a graphical representation of the SystemVerilog packing operation using streaming operators. I’ve been waiting for it since long time ago and I think the same goes for all of you. Check out Horia’s new article: >, <<)">How to Pack Data Using SystemVerilog Streaming Operators (>>, <<)