SystemVerilog standard provides structure and union data types. Jason Yu, from Intel, has tried to use them for RTL design and he shared his experience via this VerilogPro article: Using SystemVerilog Structures and Unions in a Design.
AMIQ Consulting created an UVM/SystemVerilog application that exports existing UVM register models to an IP-XACT file in order to ease IP-XACT adoption. The application is available for free under the Apache License 2. See more at UVM Register Model to IP-XACT Application