Anders Nordstrom has written one of the best articles I’ve read about the effects of over-constraining properties in formal verification. The author describes what’s safe to do and what’s not safe to do when using formal methodologies:
EDN: Anders Nordstrom: Don’t over-constrain in formal property verification (FPV) flows
High speed serial communication protocols like Ethernet, RapidIO, DisplayPort, SATA etc. implement one or more of 8b/10b encoding, 64b/66b encoding or scrambling/descrambling in the Physical Coding Sublayer. AMIQ implemented these coding algorithms and shares them as Open Source with the Verification Community:
AMIQ Blog: Physical Coding Library
Verification Gentleman shows how to use UVM internals in order to register abstract classes with UVM factory:
VerificationGentleman:Registering Abstract Classes with the UVM Factory
FPGAs are not anymore what they used to be. I’ve recently attended an online presentation by Andrew Gardner via TVS Verification Future 2016 conference. ARM is using FPGAs in an interesting manner. They’ve clustered together a lot of FPGAs to serve a common goal, that of emulating a very complex design consisting of multiple cores and various architectures. This farm of FPGAs makes it possible to verify complex designs which are otherwise impossible to be verified on simulation level. It’s also cheaper to use FPGAs compared to hardware emulation platforms provided by EDA companies. The difficult part in emulating such large designs using FPGAs is design partitioning and debug capabilities. Design partitioning needs to be done in a smart way so that updating the design affects as few FPGAs as possible. Debugging has also been improved in FPGAs with high bandwidth signal dumping capability. Another nice feature of ARMs FPGA farm is that they can remotely connect and control the FPGA farm.
I tried to offer a more detailed review, since the slides from the presentation are very much condensed and the main idea might be difficult to grasp without a live presentation of it. Here are the slides of the presentation:
ARM: FPGA accelerated IP Validation
All simulators provide these days transaction recording and visual analysis aids. Cristian presents how to use some of these features in order to speed-up debug:
CFSVision: Debugging Tip: Look At The Bubbles
A list of 7 YouTube videos on SystemVerilog and UVM from Synopsis:
Synopsis:Unleashing SystemVerilog and UVM (Series of 7 YouTube Videos)
Cadence has added in_table constraints to e-language, a concise new language construct you can use, for example to specify a random configuration space:
Cadence: Using Tables to Handle Configurability in Incisive Enterprise Specman
UVM has a lot of features, some of them not commonly used. Munjals presents the ‘uvm_barrier’ and ‘uvm_event’ classes for tasks synchronization:
Munjalm: Synchronization using UVM features
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4 Responses
Great piece of information, please add more UVM articles with working example
Hi, Taahir.
Thank you for appreciation. We constantly scan the web for new websites that may become candidates on our recommended article list. Forums like Accellera or Verification Academy are other sources of UVM code examples. If you know of any other interesting website not included here, please let us know and we’ll add it to our watch list.
Thanks,
Aurelian
Yes, there is site which I look up to regularly by Manish. http://www.learnuvmverification.com/
Please have a look.
Thanks
Taahir
Thanks for the link. We have it already on our list. Last year we’ve recommended articles from that blog, but lately it seems that the RSS feed had some problems and was not showing the latest articles. We’ll keep an eye on it.
Regards,
Aurelian