SystemVerilog interfaces are rigid constructs that don’t offer the flexibility of a class (e.g. polymorphism). Tudor Timisescu presents a recipe to create flavors of an interface, recipe which avoids turning the interface into a big, monolithic structure:
VerificationGentleman: On SystemVerilog Interface Polymorphism and Extendability
Did you ever think of functional coverage patterns?Well, our colleague Stefan Birman created a reference list of functional bitwise coverage patterns:
AMIQ Blog: Functional Coverage Patterns: Bitwise Coverage
An interesting approach of Tudor Timisescu about centralization of SVA error messages from within an interface. Controlling error messages with a fine-granularity makes use of classes inside interfaces, macros and a report catcher together with a proxy concept:
VerificationGentleman: My Take on SVA Usage with UVM
Verification is about scenarios and if you want to be effective you need to stay high on the abstraction level. LearnUVMVerification shows how to take advantage of UVM Sequences by creating sequence hierarchies:
LearnUVMVerification: The way “UVM Hierarchical Sequences” works?
Cristian Slav, a former employee of AMIQ, started a new blog on verification. In one of his articles he describes a way to translate aspect-oriented features encoded in e-language’s DNA into a mix of SystemVerilog and design patterns:
CFSVision: How To Code Efficiently In SystemVerilog Without AOP.
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