SVAUnit 2.0 Release is Available

AMIQ is pleased to announce version 2.0 of the SVAUnit framework!
Highlights of SVAUnit 2.0 release are:

• Support for sequence based scenarios
• Upgraded test setup API
• Support for complex topologies
• VPI-related API accessible through a wrapper class
• pre_test() task is now deprecated
• UVM compliance reinforced using the Verissimo SystemVerilog Testbench Linter
• SNUG-2015 paper included

Let’s go through the details of each improvement.

Support for sequence based scenarios

The API has been upgraded to support both svaunit_test and sequence-based scenario implementation.
The sequence based scenario allows users to create flexible scenarios of any complexity by chaining and/or layering sequences that are either reused from an existing library or created from scratch.
SVAUnit provides two options to run sequence based scenarios:

• In-test sequence: sequences are created/started inside a svaunit_test class

This approach allows one to drive stimulus either from a sequence and/or by directly applying stimulus to the interface.
A unit test is required to instantiate, create and start the sequence, as the following example shows:

 // Unit test used to verify the AN_SVA
class amiq_svaunit_ex_simple_test_unit extends svaunit_test;
   . . .
   // Pointer to sequence used to check a scenario
   local amiq_svaunit_ex_simple_test_sequence sequence_random;

   virtual function void build_phase(input uvm_phase phase);
      . . .
      sequence_random = amiq_svaunit_ex_simple_test_sequence::type_id::create("sequence_random", this);
   endfunction

   virtual task test();
      . . .
      sequence_random.start(sequencer);
   endtask
endclass

• Sequence-based scenario as a test

Users can also directly register sequences, which should inherit svaunit_base_sequence, as SVAUnit tests. A test class of type svaunit_sequence_test is created behind the scenes, in which the sequence with the given type is instantiated, randomized and started. The newly created test class is a specialization of svaunit_test by the sequence type.
Below you can see the definition of the sequence-specialized test class.

class svaunit_sequence_test#(type SEQ_TYPE=svaunit_base_sequence) extends svaunit_test;
   `uvm_component_param_utils(svaunit_sequence_test#(SEQ_TYPE))
   // Sequence which contains the SVA scenario
   SEQ_TYPE seq;
   ...
   // Task used to start testing - the sequence is started here
   virtual task test();
      if(!seq.randomize()) begin
         `uvm_error("SVAUNIT_SEQUENCE_TEST_RANDOMIZE_ERR",
            $sformatf("The sequence for %s could not be randomize", get_test_name()))
      end
      seq.start(sequencer);
   endtask
endclass

SVAUnit sequences are virtual sequences, meaning they can be used to control the execution of other sequences and to create a layered sequence topology.

Upgraded test setup API

We changed the add_test() method into `add_test() macro to allow registering of both unit tests and sequences.

// Register unit tests and sequences to test suite
`add_test(amiq_svaunit_ex_simple_test_unit)
`add_test(amiq_svaunit_ex_simple_test_sequence)

The `add_test(test_or_seq_type) receives as an argument the test or sequence type. When a sequence type is used, a svaunit_sequence_test#(type SEQ_TYPE=svaunit_base_sequence) is created, where SEQ_TYPE is the same as the macro argument. The newly created test’s name is the sequence’s type.
In case similar type sequences or tests need to be registered, the framework handles duplicates automatically and the resulting unit tests are named as shown below:

amiq_svaunit_ex_simple_test_sequence
amiq_svaunit_ex_simple_test_sequence@1
....
amiq_svaunit_ex_simple_test_sequence@n

Support for complex topologies

Users required to support complex topologies like several instances of the SVA container interface in one module and/or nested interfaces.
Starting with SVAUnit 2.0, the API supports addressing an SVA either by its name (in case there is a single instance of an SVA container interface) or using the SVA’s full path.
Let’s consider the following interface topology.

The SVA named SVA_1 can be address either as SVA_1 or Top.Interface_1.SVA_1, where Top is the module name used as a top, the Interface_1 is the instance name of the interface containing SVA_1.

This API upgrade allows verification of SVAs located in interfaces under deep topologies, like the one below.

VPI-related API accessible through a wrapper class

In order to provide access from both test and sequences, the entire SVAUnit API is now available using a wrapper class of type svaunit_vpi_wrapper, which inherits uvm_object. The wrapper enables access to the API from the test, sequence or sequencer through the vpiw handle, as shown in the following example.

vpiw.disable_all_assertions();
vpiw.enable_assertion("AN_SVA");
vpiw.fail_if_sva_not_succeeded("AN_SVA", "The assertion should have succeeded"); 

The reporting API is accessible as before.

pre_test() task is now deprecated

Beginning with the current version, SVAUnit 2.0, the pre_test() task has been deprecated. All signal initialization can be done at the beginning of the test() task, or respectively, inside the pre_body() or body() sequence tasks.

UVM compliance reinforced using the Verissimo SystemVerilog Testbench Linter

We have used the Verissimo SystemVerilog Linter to perform a thorough audit of the SVAUnit code sources with regards to the SystemVerilog and Universal Verification Methodology (UVM) coding requirements.
This reinforces our commitment that SVAUnit is a fully UVM compliant package.

SNUG/2015 Paper Included

AMIQ presented SystemVerilog Assertions Verification with SVAUnit paper at SNUG/UK-2015 and SNUG/Germany-2015. Both presentations were very well received by the audience, raising lots of questions. Many Thanks! to Andra Radu and Ionut Ciocirlan for their high quality work.

Where can I get the latest SVAUnit version?

You can download the latest version of the SVAUnit package from AMIQ’s github repository.

What are the next steps?

We encourage you to send us your feedback as we intend to maintain the SVAUnit library in sync with real life requirements.

About SVAUnit 1.0

SVAunit is a framework that targets SVA (SystemVerilog Assertions) verification in an isolated, simplified and standardized manner.
In April, following the presentation at CDNLive EMEA 2015, AMIQ released the first version of SVAUnit, SVAUnit 1.0. More details can be found in this article.