Do you know that the SystemVerilog LRM does not recommend calling a virtual function from within the class constructor new() function? Check out chapter 8.7
Keisuke Shimizu, from ClueLogic, explains in his UVM tutorial series, how you can use register callbacks to implement side effects inside the UVM register model:
In SystemVerilog the foreach statement can be used to iterate over the elements of an array. Special attention should be payed to loop variables (SystemVerilog