Recommended Articles – September 2016

Keisuke Shimizu, from ClueLogic, explains in his UVM tutorial series, how you can use register callbacks to implement side effects inside the UVM register model: ClueLogic: UVM Tutorial for Candy Lovers – 36. Register Callbacks

Special attention should be payed to loop variables, as their behavior depends on how the array dimensions are specified at declaration: AMIQ Blog: Gotcha: The Behavior of Foreach Loop Variables Depends on How the Array Dimensions Are Specified

Yet Another Memory Model was initially developed for modeling and managing a SystemVerilog memory. AMIQ just released YAMM 2.0 which also includes the C++ implementation: AMIQ Blog: YAMM 2.0 Release is Available

In AMIQ Resources page you can find the contents of AMIQ’s bookshelf, conference papers, various cheatsheets, recommended articles, and the blogs we periodically scan for recommended articles.


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