How to Match Strings in SystemVerilog Using Regular Expressions Recently, I needed to filter out some instance paths from my UVM testbench hierarchy. I discovered that this can be done using regular expressions and Read More Florin Oancea September 11, 2020 1 Comment
Migrating to UVM 1.2 A couple of days ago I watched a presentation on UVM 1.2 by Tom Fitzpatrick of Mentor Graphics posted on Verification Academy, and I thought Read More Florin Oancea June 6, 2014 3 Comments