Handling threads in SystemVerilog is always a challenge, especially when reset triggers. How to Decouple Threads in SystemVerilog is showing one way of decoupling a thread (task) from its originator/starter and survive the reset of its originator’s clock domain. The background here applies to DUTs which are part of more than one clock domains, thus handling multiple reset signals.
Neil Johnson(AgileSOC) presents his thoughts on how and why should one use the code coverage collected from simulations along with the one collected by formal tools. Read more in here: Why Simulation Code Coverage and Formal Code Coverage are the Same. I encourage you to also go through the comments.
This is a new kind of topic for our blog, but still very interesting to read about: Hacking and AI. How would it be if hacking is not done by humans anymore, but by AI bots? Yoav Hollander (the guy who invented e-Language and the modern metric driven verification) posts his ideas on how to verify AI systems (considering also the new GPT3). He recommends a paper written by Bruce Schneier – The coming AI hackers. That’s a 50 page article, but Yoav assures us that it is easy to read and it is worth reading it. A prelude of the full-paper can be found in a short article on wired: Hackers Used to Be Humans. Soon, AIs Will Hack. 
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