Did you know that you can match strings using regular expressions from within SystemVerilog code? UVM implements a function called uvm_re_match. My colleague, Florin Oancea, explains how to use it and what you should pay attention at: How to Match Strings in SystemVerilog Using Regular Expressions
In the August edition of the recommended articles I mentioned a challenge launched by Neil Johnson. The answers to this challenge are now posted by Dave Rich in his SystemVerilog Race Condition Challenge Responses article. It is a good reference on what NOT to do when writing RTL or TB code.
Recently, I learned about an emerging and impressive AI System called GPT-3. This GPT-3 (Generative Pre-trained Transformer 3) is an autoregressive language model that uses deep learning to produce human-like text. David Chalmers, an Australian philosopher, described GPT-3 as “one of the most interesting and important AI systems ever produced”.
GPT-3 was used to write the following article. Can you distinguish it from a human being? A robot wrote this entire article. Are you scared yet, human?.
But how is this GPT-3 system being verified? Yoav Hollander, already started to think about its verification: GPT-3 and verification.
A LinkedIn post from Yousef B. Bedoustani, pointed out how same hardware design problem approached with two different mentalities can lead to very different solutions: RTL vs. Software Mentality in FPGA/ASIC Design; Latency From 161 to 2 Clock Cycle!
The FOSSI foundation announced that you can now produce your own physical chips. For free. In the Open. The “open” part is guaranteed by the open source PDK (Process Design Kit) called Skywater PDK. The “free” part is guaranteed by Google and efabless.
They are providing completely free of cost chip manufacturing runs: one in November this year, and multiple more in 2021. All open source chip designs qualify, no further strings attached!
May your ASIC come true!