Ben Cohen, a leading expert on SystemVerilog Assertions (SVA), wrote an article about Concurrent Assertions and their limitations when it comes to using delays inside SVAs. He also shows how to replace complex assertions with tasks. In the end, he points it out nicely: “implementing an assertion with tasks is acceptable; SVA is just a shorter notation that adapts well for most cases, but not all cases.” Read it all in SVA Alternative for Complex Assertions
Teo from AMIQ, implemented another nice feature which brings the coverage concept from HVL (Hardware Verification Languages) into C++ language. It already gained a fan. Read it all here: C++ Implementation of Functional Coverage for SystemC
If you were ever curious what is new in the SystemVerilog IEEE Std.1800-2017 standard compared to the one from 2012, then this is the article to read from Verilab: Thoughts on the updated standard, by Principal Consultant Jonathan Bromley
2 Responses
For simple assertions, dynamic delays and repeats can also be expressed using a sequence defined in a package.
package sva_delay_repeat_pkg;
sequence dynamic_repeat(q_s, count);
int v=count;
(1, v=count) ##0 first_match((q_s, v=v-1’b1) [*1:$] ##0 v<=0);
endsequence
sequence dynamic_delay(count);
int v;
(1, v=count) ##0 first_match((1, v=v-1'b1) [*0:$] ##1 v dynamic_repeat(q1, r) ##1 c);
ap_delay:assert property(a |-> dynamic_delay(r) ##0 b);
http://SystemVerilog.us/vf/sva_delay_repeat_pkg.sv // package
http://SystemVerilog.us/vf/sva_delay_repeat.sv // testbench
Thank you for the extra hint, Ben.