Open Source Summer School Labs

The last Digital Circuits Simulation and Verification summer school made me wonder: why restrict access to the labs to only those students that can join the summer course? why not give access to the labs to any student that wished to take the course but couldn’t join due to various reasons?

That is why I decided to open the summer school labs to the verification community (i.e. academia, companies etc) under Apache License 2.0. You can download these from the dedicated GitHub repository.

The labs are designed to aid the explanation of various SystemVerilog, UVM and functional verification concepts. The Verilog implementation used is not necessarily the best and is most probably not usable in real-life projects. Indeed, its sole purpose is to give students the full experience of pre-silicon functional verification.

You can take the labs and follow them through using the simulator provided by your company/faculty, a student licensed simulator (e.g. ModelSim™) or even

As things currently stand, the labs differ in terms of complexity and have the following goals:

  • Verilog design and simulator usage knowledge refresh
  • Learning functional verification concepts without an RTL DUT
  • Learning functional verification concepts with an RTL DUT

All exercises are DVT Eclipse IDE-ready in order to accelerate language and methodology learning.
We plan to update these labs and to integrate your feedback (e.g. bug fixing, documentation enhancements, etc.) and also to answer user questions. Your feedback and contributions are invaluable and will help to make the labs better to use for others. Future releases will be announced on this blog.



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