August is synonymous with vacation in many parts of the world, but not for everyone as you can see.
Cristian shows how to implement the mechanism which allows UVM registers to be sensitive to more than one reset signal:
CFSVision: SystemVerilog: How To Model Multiple Reset Signals in UVM Registers
Tudor has a quick look at the SVAUnit library: VerificationGentleman: A Quick Look at SVAUnit
Manish started a series of tutorials on SystemVerilog OOP (Object Oriented Programming) concepts like: class, objects, class constructor, class properties/methods, Copying Handles, copying objects, shallow copy, deep copy, static variables/methods, inheritance, polymorphism. They are a nice memory refreshment or a good starting point for people not used to OOP.
The latest article of the AMIQ – Gotcha series, illustrates what happens in SystemVerilog if static keyword is used both before and after the function or task keywords:
AMIQ – Gotcha: “static” function/task in SystemVerilog
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