Recommended Articles – May 2016

Horia Enescu from AMIQ, started a series of posts that present how to implement flexible coverage definitions in SystemVerilog (Part 1 and Part 2). Horia uses option.weight and with-clause to allow coverage definitions to adapt to item’s bin range.

New entry on our list VerificationSudha encourages UVM dissection and brings to surface internal information about UVM: Part I and Part II.

Error handling in serial communication is a complex task and so is verifying it. If you are new to error scenarios, I definitely recommend reading these series of articles from VerificationSudha: understanding errors, creating a plan and prioritize error scenarios, defining error capabilities of the verification environment, implementing error injection capability, creating directed and random tests and writing coverage for verification closure definition.

Manish Singhal, from LearnUVMVerification wrote three more articles: UVM phasing in UVM1.2, How to finish an UVM test and what are the Debug tools within UVM.

VerificationGentleman, continues his odyssey with SystemVerilog reflection API. In Part 1 he described how to create a reflection manager using DPI and VPI. In Part 2 he wrestles with language or compiler limitations, and in the end he achieves his goals to get and set the variables of a class.