New entry on our list, Jason Yu impressed us with his eloquent and easy to follow style. He shares his opinion on how Verilog constructs should be used:
VerilogPro: Verilog twins: case, casez, casex. Which Should I Use?
VerilogPro: One-hot State Machine in SystemVerilog – Reverse Case Statement
LearnUVMVerification presents the interaction between UVM driver and UVM sequences:
LearnUVMVerification: UVM Driver Use Models – Part 1
Stefan Birman presents his impressions on FDL Conference(Forum on specification and Design Languages):
AMIQ Blog: A Conference to Attend: Forum on Specification and Design Languages
The VerificationGentleman had some fun trying to solve the Einstein’s Five House Riddle in SystemVerilog and it seems that Sandeep Gor followed along and made a solution for the e-language. I had taken Sandeep’s challenge and found an optimized version for e-language which will be published soon on our blog.
DigitalVerification: Einstein’s Five House Riddle – Solution in ‘e’
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