Keisuke Shimizu (ClueLogic) adds some sugar to the tasteless world of UVM messaging and serves it heavily garnished with pictures and detailed, well structured, explanations:
ClueLogic: UVM Tutorial for Candy Lovers – 27. Reporting Verbosity
ClueLogic: UVM Tutorial for Candy Lovers – 28. Message Logging
Puneet Goel, inventor of vLang, describes the effect of hiding a variable from the parent class with respect to polymorphism:
SystemVerilog.net: Variable hiding considered harmful
Ilia Davidovich, a new entry on our radar, explains polymorphism:
SystemVerilogTips: Polymorphism in SystemVerilog
Copy&Paste “hero” carries his own daemon that usually lurks on the last line in a modified block of a pasted code. Andrey Karpov (Intel) lays out a convincing article about the peculiar last line-effect:
Intel: The Last Line Effect
Tudor connects the dots between coverage and constraints and presents a solution for keeping constraint and coverage ranges in sync with virtually no effort:
VerificationGentleman: Keeping Constraints and Covergroups in Sync
Be aware!!! This solution trespasses the separation of concerns and can hide generation constraints or coverage definition errors. As long as you implement generation and coverage as separate concerns you still have a chance to discover unintentional errors in either of them and/or in RTL. Molding coverage definitions to generation constraints eliminates the natural safety net of generation vs coverage implicit checking.
Cristian Slav (AMIQ) reveals that randomization of object-type fields is achieved only if the object handle is not null:
AMIQ Blog: Gotcha: Using “rand” Modifier for Object Handles is not enough!
Efrat Shneydor (Cadence, TeamSpecman) presents how to customize the behavior of a deep_copy() command from within e-Language code:
Cadence: Specman deep_copy()—Creating Too Many Structs
Enjoy the selection! and… don’t forget to use sunscreen!
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