amiq_dcr – SystemVerilog UVC for DCR Protocol

AMIQ released the amiq_dcr UVC on GitHub
The UVC is available to the verification community for free under the Apache License 2.

The purpose of the amiq_dcr UVC is to model the Device Control Register Bus (DCR) protocol, supporting all the features of the protocol such as:

  • 4-cycle minimum read or write transfers extendable by slave or master
  • Handshaking supports clocked asynchronous transfers
  • Slave bus timeout inhibit capability
  • Privileged and Non-Privileged transfers

The amiq_dcr UVC also includes documentation, self checking tests and usage example.
The amiq_dcr UVC is build on top of Common Agent (cagt) architecture available on GitHub.

Feel free to download, use and contribute.


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