High speed serial protocols transmit or receive data on a 2xN-wire bus that usually does not include the clock signal. Each device must recover the clock out of the incoming data traffic. Deepak Nagaria explains how clock recovery works:
ArrowDevices: Beginners Guide To Clock Data Recovery
There are RTL designs which make use of two registers behind the same address (one register is used for read access and the other for the write access). How would you verify such a set of “twin registers”? See Tudor Timisescu’s solution in his new article on the vr_ad register model series:
VerificationGentleman: vr_ad Twin Registers
Any IT passionate must have tried, at least once, sniffing the Ethernet link by using a network protocol analyzer. Wireshark is such a tool and Cristian Slav makes use of it in order to verify an RTL design or a VIP. As a test environment, Cristian uses the Ethernet library available on AMIQ’s Github:
AMIQ Blog: How to Inspect Ethernet Packet Streams with Wireshark
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