Working in a multi-language environment makes you hit this scenario: I model some data using a “when” subtype in e-language, how do I transfer that data over to a SystemVerilog component? The answer to the question is found here:
Cadence: Transferring e “when” Subtypes to UVM SV via TLM Ports—UVM-ML OA Package
When you wonder if a certain SystemVerilog language construct can reside inside another one use this article as your quick reference:
AMIQ Consulting Blog: What Goes where in SystemVerilog?
A common annoyance in SystemVerilog is making sure that enumerated type name (literals) are unique. Tudor presents a few ways to encapsulate enumerated type literals:
VerificationGentleman: A New Twist on SystemVerilog Enumerated Types
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