Recommended Articles – September 2014

SystemVerilog does not support multiple class inheritance, but there are ways to emulate it. Tudor Timisescu shows one way:
VerificationGentleman: Fake It ’til You Make It – Emulating Multiple Inheritance in SystemVerilog

Is your verification environment using multi-language verification components? Do you need to synchronize the end of test objections? Cadence illustrates how to sync the objection mechanism between verification components written in SystemVerilog and e-language:
Cadence: Objection Mechanism Synchronization Between SystemVerilog and e Active Verification Components

If you need backdoor UVM register access in SystemVerilog, this article is a good reference:
ClueLogic: UVM Tutorial for Candy Lovers – 24. Register Access through the Back Door

Ignoring bins from a cross coverage can be a tedious work if you don’t know about some 2012 SystemVerilog constructs. Aurelian illustrates these constructs with some examples:
AMIQ Consulting Blog: How to Ignore Cross Coverage Bins Using Expressions in SystemVerilog

In AMIQ Resources page you can find the contents of AMIQ’s bookshelf, conference papers, various cheatsheets, recommended articles, and the blogs we periodically scan for recommended articles.


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