Zebra Puzzle is a very good didactic problem for understanding constraints. Tudor Timisescu, the blog’s author, takes the effort in showing us what problems he encountered while building the constraints in SystemVerilog.
Verification Gentleman: Fun and Games with CRV: The Zebra Puzzle
If you want to know how to constraint elements of a dynamic array from System Verilog, here it is a place for a quick reference:
Verification Gentleman: The Not So Comprehensive Guide to SystemVerilog Array Constraints
Have you ever wondered what’s the finish criteria of a task when working with Agile methodology? Have you thought about using Kanban techniques in hardware verification? You can find some answers in this article:
AgileSOC: Kanban For One… The Verification Engineer Edition
A good exposure of clock-domain-crossing (CDC) verification challenges:
EDACafe Blogs: Fundamentals of Clock Domain Crossing Verification
A method to decrease the over-repeating painful effort in analyzing regression results:
AMIQ Consulting Blog: Save Time in Pre-Silicon Functional Verification Using Regression Automation Scripts
A hot discussion about how to determine programming languages’ productivity when writing code in HVL (Hardware Verification Languages) like e language or System Verilog language. Blake French, who started the topic tries to look into software world academics and extract measure points for HVLs. It’s interesting to see the feedback he got (you need a LinkedIn account):
LinkedIn Specman User Group: Productivity of Programming Languages
Are you done? The ultimate question a verification engineer receives from his/her manager:
AgileSOC: The 90% Done Myth
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