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How to Pack Data Using the SystemVerilog Streaming Operators (>>, <<)

The verification of digital circuits requires dealing with bits and bytes. It is not a trivial thing to pack or unpack bits, bytes, half words,

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AMIQ Consulting May 29, 2017 25 Comments

How to Pack Data Using the SystemVerilog Streaming Operators (>>, <<)

The verification of digital circuits requires dealing with bits and bytes. It is not a trivial thing to pack or unpack bits, bytes, half words,

Read More
AMIQ Consulting May 29, 2017 26 Comments

How To Reduce the Number of VIP Instances using Accessor Classes

In this post I demonstrate how to use parameterization and accessor classes in order to reduce a variable number of VIP instances to a single

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Stefan Birman May 9, 2017 No Comments
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