Recommended Articles – February 2023

 Handling threads in SystemVerilog is always a challenge, especially when reset triggers. How to Decouple Threads in SystemVerilog is showing one way of decoupling a

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Recommended Articles – January 2023

SystemVerilog/UVM code reuse is reaching the next level. Andrei Vintilă and Sergiu Duda have developed a framework/architecture called Externally Controlled Testbench (aka ECTB), initially presented

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