functional verification Archives - Page 2 of 11

Digital Circuits Simulation and Verification Summer School

The 2018 Digital Circuits Simulation and Verification Summer School took place 9th-13th of July. There were 16 participants, a big step forward compared to previous

Stefan Birman July 17, 2018 No Comments

How To Customize UVM Sequencer’s Arbitration Policy

This post shows how you can implement a custom sequencer arbitration policy in UVM. The example considers a sequence that contains a field called seq_type:

Stefan Birman October 6, 2017 No Comments

Amiq Education Program Updates Summer 2017

I just came back from vacation and my fingers are restless, urging me to share with you some of the Amiq Education Program’s latest activities.

Stefan Birman August 1, 2017 No Comments