This course has been developed together with AMIQ Consulting and is the second successful project to come out of the AMIQ Education Program, the first being the Digital Circuits Simulation and Hardware Verification summer courses in 2015 and 2016. AMIQ’s contribution consists of the design and review of course materials and practical exercises, as well as the delivery of some of the lectures on-site in Timișoara. On 12 October I gave lectures on SystemVerilog Language Basics and Verification Planning; on 9th of October I gave a lecture on Verification Metrics.
A Brief History
In November 2015, Asst. Prof. Oana Boncalo and Asst. Prof. Alexandru Amaricăi, both teachers at the Politehnica University of Timișoara, invited me to give a lecture to their students on choosing a career path in the semiconductor industry with a focus on functional verification. The lecture was supposed to last two hours, but as the students showed a lot of interest, I extended it to four.
At the end of May of this year, Asst. Prof. Oana Boncalo told me they were planning to teach a Pre-Silicon Verification course starting in the fall, which was kind of expected. We worked on the course support materials over the summer and now it’s ready to be delivered to the students. And so here we are today.
About the Verification and Validation of Hardware Systems Course
The course is designed for 4th year students who have already completed the Object Oriented Programming and Digital Design courses and have finished their practical digital design applications. It lasts for one semester and is made up of 14 two-hour lectures with an additional 28 hours of lab work.
The course structure is as follows:
- C1: Introductory course: Industry trends, Verification Cycle
- C2: The anatomy of a verification environment
- C3: SystemVerilog: data types, procedural statements & routines
- C4: SystemVerilog: Interfaces, modports, logic vs. wire, clocking blocks, always blocks & programs, clock and reset generation
- C5: Threads and Interprocess Communication
- C6: Refresher on Basic OOP (inheritance, static and singleton classes, callbacks, blueprint patterns), Verification Components
- C7: Constrained Random Data Generation
- C8: Verification Metrics: Code Coverage, Functional Coverage, Assertion Coverage
- C9: Checks, Tests and the Verification Cycle
- C10-C11: SystemVerilog Assertions
- C12-C14: UVM & Case Study
The practical component of the course covers the following areas:
- Use of digital simulator for verification
- SystemVerilog Types
- SystemVerilog Classes and Constrained Random Generation
- How to link the Verification Environment with the simulator
- Definition of coverage metrics
- Implementation of data checks and scoreboards
- Implementation of SystemVerilog Assertions
- Creation of a basic UVM-SystemVerilog verification environment
- Creation of tests
The course makes use of the Digital Design lab infrastructure, which has 20 places. Students will use the ModelSim simulator for their practical exercises.
So far 30 students have enrolled for this course.
Although I expect it will take a number of iterations to “polish” the course materials, I believe the course has already got off to an excellent start. The energy and dedication everyone has put into it has laid strong foundations: the course support materials contain in-depth, well-structured information, balanced exercises and an easy-to-follow grading system.
Oana Boncalo, Assistant Professor at Politehnica University of Timișoara
Timișoara is a high-tech hub that attracts some of Europe’s biggest software and hardware companies (e.g. Alcatel-Lucent, Continental, Movidius, BitDefender and ACI). The new course is designed to complement the existing Digital Design course and helps us meet industry requirements in terms of the knowledge and experience of our Electronics graduates. It appeals to both companies and graduates for clear economic reasons: there are a lot of job opportunities in the field of verification waiting to be snapped up by those who do this course. The university has a lot to gain as well: the better the university is able to meet industry expectations, the more attractive it will become to students and private investors.
There are also other reasons to introduce a pre-silicon verification course: engineers that only complete a course in Digital Design are left with an incomplete image of the ASIC design cycle, which can lead to buggy designs. What’s more, the verification principles the students will learn can also be applied in areas such as embedded systems, FPGA-based systems and low-level software development.
About the course: I have a particular interest in the area of Assertion-Based Verification (ABV) and SystemVerilog Assertions (SVAs). This chapter of the course also provides a strong foundation for formal verification. I use ABV extensively to verify LDPC decoder sub-blocks and interface protocol compliance. SVAs provide a beautiful, synthetic way to express a design’s intention and I think students will appreciate their simplicity and “mathematical” structure.
Another interesting chapter is that on Verification Metrics, which provides students with the means to exercise control over the verification progress.
Alexandru Amaricăi, Assistant Professor at Politehnica University of Timișoara
I have collaborated with Oana Boncalo on a number of research projects covering a range of subjects, such as floating point arithmetic, LDPC decoder design and FPGA accelerators for data center applications. Our most recent research project set out to find an optimal implementation for Low-Density Parity Code (LDPC) decoders and involved design, verification and implementation on a Xilinx Zynq FPGA platform.
This course complements our existing curriculum and will in the future help us to develop internally, i.e. within the department, the necessary verification resources our research programs require. This means the results of our research will be more reliable and more appealing to private investors.
About the course: I have a particular interest in the area of functional verification, especially using UVM/SystemVerilog. My experience of verifying LDPC decoders using UVM-SystemVerilog was a good preparation for the course. The software design patterns used in UVM can appeal to students more interested in software than hardware.
Another interesting chapter is that on Constrained Random Data Generation, which provides students with the means to create interesting scenarios, while at the same time keep things simple and manageable.
About the AMIQ Education Program
AMIQ Education Program started in October 2014. The aim of the AMIQ Education Program is to promote the field of pre-silicon verification in the academic world, among universities and students alike, and to help universities keep in sync with industry requirements. The AMIQ Education Program is primarily focused on Romanian universities, but is also open to collaborations with foreign universities.
The AMIQ Education Program comprises the following:
- Pre-Silicon Verification Course Delivery: we deliver semester courses and intensive hands-on courses
- Pre-Silicon Verification Course Development Support: we support teachers in developing course support materials, practical exercises and the set-up of lab infrastructure
- Career Path Development: we deliver career path workshops and student mentoring
- Co-operative Education: we provide internships and BSc/MSc thesis support
For more information about the program you can write us here.