Functional Verification Planning and Management
We are recognised for our high quality verification services and customer responsiveness since 2003.
About Amiq Consulting
We provide our clients with a solid base of expertise in hardware design verification, built since 2003. Our clients operate in industries like automotive, telecommunications, and computer peripherals.
We combine a deep knowledge of hardware design verification, languages, methodologies, and tools with extensive project experience to help our clients deliver complex designs on time, within a budget and infrastructure constraints.
Services
Ramp-up
and Qualification
Due to the very high clock cycle consumption of System Level Verification, the planning and implementation of the verification process needs to be done carefully. The verification process requires in-depth planning, advanced verification skills like object-oriented language programming (SystemVerilog, C++/SystemC) and methodology awareness (UVM), as well as a creative approach to problem solving.
We have the expertise to provide system-level verification services for complex SoCs, involving working with various hardware and software IPs and using specific tools like hardware acceleration and hardware emulati…
Ramp-up
We have been successful at rescuing projects that have gone off track. We start by identifying the project bottlenecks. We then define a rescue strategy and implement it. We analyze performance periodically and continue to refine our strategy taking into account all internal and external factors until the project is back on track.
Our ramp-up services include infrastructure setup, template creation, methodology/flow definition and implementation, and resource planning. We can also perform interviews to assist with hiring new team members.
and Qualification
We can develop verification IPs (VIPs) on demand, for any protocol or function, by using any one of the HVLs (e, SystemVerilog) or assertion languages (SVA, PSL).
Normally, the client provides us with the protocol or function specification and we deliver the code, documentation, suites of tests, regression reports and scripts. The deliverables are prioritized according to client’s requirements and schedule in such a way that the integration work can start before the final release of the VIP…
We provide on-site and off-site training services for a broad range of hardware verification languages and methodologies.
The training is delivered by senior consultants with comprehensive experience of working on a range of different projects with top companies.
SERVICES
Ramp-up
and Qualification
Due to the very high clock cycle consumption of System Level Verification, the planning and implementation of the verification process needs to be done carefully. The verification process requires in-depth planning, advanced verification skills like object-oriented language programming (SystemVerilog, C++/SystemC) and methodology awareness (UVM), as well as a creative approach to problem solving.
We have the expertise to provide system-level verification services for complex SoCs, involving working with various hardware and software IPs and using specific tools like hardware acceleration and hardware emulati…
Ramp-up
We have been successful at rescuing projects that have gone off track. We start by identifying the project bottlenecks. We then define a rescue strategy and implement it. We analyze performance periodically and continue to refine our strategy taking into account all internal and external factors until the project is back on track.
Our ramp-up services include infrastructure setup, template creation, methodology/flow definition and implementation, and resource planning. We can also perform interviews to assist with hiring new team members.
and Qualification
We can develop verification IPs (VIPs) on demand, for any protocol or function, by using any one of the HVLs (e, SystemVerilog) or assertion languages (SVA, PSL).
Normally, the client provides us with the protocol or function specification and we deliver the code, documentation, suites of tests, regression reports and scripts. The deliverables are prioritized according to client’s requirements and schedule in such a way that the integration work can start before the final release of the VIP…
We provide on-site and off-site training services for a broad range of hardware verification languages and methodologies.
The training is delivered by senior consultants with comprehensive experience of working on a range of different projects with top companies.
Blog
UVM Packer Size Limitation: The 4KB Problem
In UVM-based verification environments, uvm_packer is a powerful utility for converting class objects to bit streams and vice versa. It’s commonly used for serialization and
Accessing elements in an array of interfaces
Accessing elements of instance arrays in SystemVerilog requires elaboration-time constants, which can limit flexibility and scalability. Using generate constructs or virtual interfaces helps overcome these
Recommended Articles – March 2025
Hi there! Our colleague Andrei wrote last month a verification article about how to accelerate the debugging process in verification by using error clustering. You can
UVM Packer Size Limitation: The 4KB Problem
In UVM-based verification environments, uvm_packer is a powerful utility for converting class objects to bit streams and vice versa. It’s commonly used for serialization and
Accessing elements in an array of interfaces
Accessing elements of instance arrays in SystemVerilog requires elaboration-time constants, which can limit flexibility and scalability. Using generate constructs or virtual interfaces helps overcome these
Recommended Articles – March 2025
Hi there! Our colleague Andrei wrote last month a verification article about how to accelerate the debugging process in verification by using error clustering. You can
INDUSTRIES
Our verification services address the niche of Home Appliances, a class of ASIC/FPGA applications that target smart home devices, multimedia streaming devices, smart TVs, fiber-to-the-home modems, etc. The perceived value of home applications is particularly sensitive to the TCO, which includes poor quality or user experience incurred costs. AMIQ engineers use formal and functional verification to eliminate functional bugs, focusing on features and scenarios that directly impact the user experience. We also proactively go a long way to make sure the architectural and implementation decisions do not negatively impact the user experience.
Industry 4.0 is used in smart manufacturing, smart cities, smart power grids, smart agriculture, smart digital supply chains, and more. These IoT applications bring together a mix of hardware and Cloud software to achieve wireless sensing, automation, and control. The IoT hardware must fulfill tough constraints on miniaturization and power efficiency, since they are a perfect match for dedicated ASICs. AMIQ engineers use metric-driven verification to ensure that [ultra]low power constraints are complied with and dead code or redundant functions don’t slip in the final product.
In telecom applications such as PON / WiFi networks, terabit switches, xG mobile networks, etc. the Quality of Service (QoS = throughput, latency, uptime) is only one of the concerns. Besides that, telecom systems must deliver reliable digital services continuously for long periods of time, sometimes under extremely difficult environmental conditions in hard-to-access locations. This elevates low power, over-the-air reconfigurability and remote debuggability features from nice to have to a must. Thus, AMIQ engineers elevate the verification focus from subsystem level to SoC and system level to ensure that HW and SW converge on the delivery of all the aforementioned features.
The rise of electrical mobility and driving automation (i.e. L3-L5 autonomous driving) expanded the usage of ASIC/SW stacks as reliable solutions for life-critical applications. The perception, localization, planning and control layers of an L3/L4/L5 autonomous driving stack must be fault tolerant and operate in real-time while considering unreliable access to the network. In order to comply with such constraints the architects of autonomous driving stacks push as much of the stack as possible into ASICs or FPGAs, increasing the role of pre-silicon verification. Besides the deployment of ISO26262 for supporting features, we do metric-driven functional verification of the RTL implementation of neural networks, planning and decision algorithms. AMIQ verification flow assures full traceability of the verification metrics from the algorithm model to the signed-off RTL, allowing customers to investigate early potential points of failure in the productization of the concept.
Increasing renewable energy capacity requires on-the-fly management of the network load, smart (dis)charging of storage systems and early warnings about the aging of components. This is achieved by a complex network of sensors and actuators that are orchestrated by a central management system. SoCs that sustain these systems fall in the category of IoT applications, but with a tweak: they must also be insensitive to strong EM interference. AMIQ engineers follow through the core verification concerns of any IoT system, while assuring that the used protocols and supporting HW are insensitive to random errors that could be induced by strong EM fields. Also, in the case of battery management ASICs, we make sure that SoC’s power domains and their (de)activation are coordinated, at the right points in time.
INDUSTRIES
Our verification services address the niche of Home Appliances, a class of ASIC/FPGA applications that target smart home devices, multimedia streaming devices, smart TVs, fiber-to-the-home modems, etc. The perceived value of home applications is particularly sensitive to the TCO, which includes poor quality or user experience incurred costs. AMIQ engineers use formal and functional verification to eliminate functional bugs, focusing on features and scenarios that directly impact the user experience. We also proactively go a long way to make sure the architectural and implementation decisions do not negatively impact the user experience.
Industry 4.0 is used in smart manufacturing, smart cities, smart power grids, smart agriculture, smart digital supply chains, and more. These IoT applications bring together a mix of hardware and Cloud software to achieve wireless sensing, automation, and control. The IoT hardware must fulfill tough constraints on miniaturization and power efficiency, since they are a perfect match for dedicated ASICs. AMIQ engineers use metric-driven verification to ensure that [ultra]low power constraints are complied with and dead code or redundant functions don’t slip in the final product.
In telecom applications such as PON / WiFi networks, terabit switches, xG mobile networks, etc. the Quality of Service (QoS = throughput, latency, uptime) is only one of the concerns. Besides that, telecom systems must deliver reliable digital services continuously for long periods of time, sometimes under extremely difficult environmental conditions in hard-to-access locations. This elevates low power, over-the-air reconfigurability and remote debuggability features from nice to have to a must. Thus, AMIQ engineers elevate the verification focus from subsystem level to SoC and system level to ensure that HW and SW converge on the delivery of all the aforementioned features.
The rise of electrical mobility and driving automation (i.e. L3-L5 autonomous driving) expanded the usage of ASIC/SW stacks as reliable solutions for life-critical applications. The perception, localization, planning and control layers of an L3/L4/L5 autonomous driving stack must be fault tolerant and operate in real-time while considering unreliable access to the network. In order to comply with such constraints the architects of autonomous driving stacks push as much of the stack as possible into ASICs or FPGAs, increasing the role of pre-silicon verification. Besides the deployment of ISO26262 for supporting features, we do metric-driven functional verification of the RTL implementation of neural networks, planning and decision algorithms. AMIQ verification flow assures full traceability of the verification metrics from the algorithm model to the signed-off RTL, allowing customers to investigate early potential points of failure in the productization of the concept.
Increasing renewable energy capacity requires on-the-fly management of the network load, smart (dis)charging of storage systems and early warnings about the aging of components. This is achieved by a complex network of sensors and actuators that are orchestrated by a central management system. SoCs that sustain these systems fall in the category of IoT applications, but with a tweak: they must also be insensitive to strong EM interference. AMIQ engineers follow through the core verification concerns of any IoT system, while assuring that the used protocols and supporting HW are insensitive to random errors that could be induced by strong EM fields. Also, in the case of battery management ASICs, we make sure that SoC’s power domains and their (de)activation are coordinated, at the right points in time.
Careers @AMIQ Consulting
Junior Verification Engineer
We are looking for a Jr. Verification Engineer with good electronics background and practical object-oriented software knowledge to be trained for the functional hardware verification
Junior Verification Engineer
We are looking for a Jr. Verification Engineer with good electronics background and practical object-oriented software knowledge to be trained for the functional hardware verification
Get in touch with Amiq Consulting
